Consulting and design services for the project Concept development of a Design-for-Test

The two projects named above are cyber-security applications to fullfill requirements for the European Cyber-Security-Act. They will be developed in 22 nm FD-SOI silicon technology and beyond. To assure testability on block level up to system on chip top level, a strategy for DFT insertion and simulation must be developed and implemented. Therefore, one meeting per quarter shall be performed at the Fraunhofer Institute for Integrated Circuits in Erlangen-Tennenlohe. Furthermore, flexibility of working hours is required in order to be able to react promptly to urgent adjustments.